1. Field of the Invention
The present invention relates to a display device and a method of fabricating a display device, and more particularly, to a liquid crystal display device and a method of fabricating a liquid crystal display device.
2. Description of the Related Art
In general, a liquid crystal display (LCD) device displays images corresponding to video signals on a liquid crystal display panel using liquid crystal cells arranged in a matrix configuration to adjust light transmission ratios according to the video signals. Accordingly, the liquid crystal cells are arranged in an active matrix form and are driven using integrated circuits (ICs). The driving ICs are commonly fabricated as an IC chip and are mounted on a tape carrier package (TCP) in case of a tape automated bonding (TAB) method, or the ICs are mounted on a surface of the liquid crystal display panel in case of a chip-on-glass (COG) method. In the TAB method, the driving ICs are electrically connected with a pad portion disposed on the liquid crystal display panel by the TCP.
FIG. 1 is a plan view of a liquid crystal display panel according to the related art. In FIG. 1, a liquid crystal display panel includes an active region 10 in which liquid crystal cells are aligned in a matrix configuration, and a gate pad portion 6 and a data pad portion 8 are positioned along a marginal region of a lower substrate 2. The marginal region of the lower substrate 2 does not overlap with an upper substrate 4, and the gate and data pad portions are connected with gate lines 1 and data lines 5, respectively. In the active region 10 of the lower substrate 2, the data lines 5 receive video signals and the gate lines 1 receive gate signals are positioned to cross each other. In addition, a thin film transistor (TFT) for switching the liquid crystal cells and a pixel electrode that is connected to the TFT for driving the liquid crystal cell are formed at the intersection of the gate and data lines 1 and 5. Although not shown, a black matrix, color filters, and a common electrode are formed on the upper substrate 4.
Then, the upper substrate 4 and the lower substrate 2 are attached by a sealant pattern coated within a sealant region 12 that is positioned along a perimeter of the active region 10. Accordingly, a predetermined cell gap is formed between the upper substrate 4 and the lower substrate 2 having a height equivalent to the sealant pattern. Next, liquid crystal material is filled into the predetermined cell gap. In addition, spacers may be included within the predetermined cell gap before injection of the liquid crystal material.
FIG. 2 is a partially enlarged view of a gate link region of FIG. 1 according to the related art, and FIG. 3 is a cross sectional view along I-I′ of a sealant region in FIG. 2 according to the related art. In FIGS. 2 and 3, a gate link portion 15 extends from a gate pad portion 14 and includes a gate link electrode 16. Disposed above the gate link electrode 16 are a gate insulating layer 22, an amorphous silicon layer 24, an n+ doped silicon layer 26 (n+ layer), and a passivation layer 28.
The gate link electrode 16 is integrally formed with the gate pad 14 and gate line (not shown) by patterning gate metal materials deposited on the transparent substrate 20. Then, the gate insulating layer 22, the amorphous silicon layer 24, and the n+ layer 26 are sequentially deposited, and the n+ layer is patterned. Next, the passivation layer 28 is sequentially deposited thereon. Then, in order to prevent electrical shorting and interaction by the amorphous silicon layer 24 between the gate pad portion 14 and the gate link portion 15, the gate insulating layer 22, the amorphous silicon layer 24, the n+ layer 26 and the passivation layer 28 are simultaneously etched to expose a portion EA of the transparent substrate 20.
Next, the sealant pattern 30 is coated along a direction crossing the gate link portion 15. Since stepped portions are created within the exposed portions EA of the transparent substrate, a uniform cell gap cannot be obtained by the sealant pattern 30.
FIG. 4 is a partially enlarged view of a data link region in FIG. 1 according to the related art, and FIG. 5 is a cross sectional view along II-II′ of the sealant region in FIG. 2 according to the related art. In FIGS. 4 and 5, a data link portion 33 extends from a data pad portion 32 and includes a gate insulating layer 22. In addition, the data link portion 33 includes an amorphous silicon layer 24, an n+ layer 26, a data link electrode 34, and a passivation layer 28.
After sequentially depositing the gate insulating layer 22 on a transparent substrate 20, the amorphous silicon layer 24 and the n+ layer 26 are deposited on the gate insulating layer 22. Then, the n+ layer is patterned and data metal materials are deposited thereon. Next, the data link electrode 34 is integrally formed with the data line and the data pad 32 by patterning the data metal materials. Then, the passivation layer 28 is formed over the data link electrode 34.
In order to prevent electrical shorting and interaction by the amorphous silicon layer 24 between the data pad portion 32 and the data link portion 33, the gate insulating layer 22, the amorphous silicon layer 24, the n+ layer 26, and the passivation layer 28 are simultaneously etched to expose a portion EA of the transparent substrate 20. Then, a sealant pattern 30 is coated along a direction crossing the data link portion 33. Accordingly, since stepped portions are created within the exposed portions EA of the transparent substrate 20, a uniform cell gap cannot be obtained by the sealant pattern 30.
FIG. 6 is a cross sectional view along III-III′ of a liquid crystal injecting side in FIG. 1 according to the related art. In FIG. 6, a liquid crystal injecting side in which a plurality of signal lines, such as common electrode lines and the like, are positioned includes the gate metal layer 16, the gate insulating layer 22, the amorphous silicon layer 24, the n+ layer 26, and the passivation layer 28, wherein the sealant pattern 30 is coated on the passivation layer 28.
Accordingly, the stepped portions that exist in the exposed portions EA of the transparent substrate 20 do not exist in the liquid crystal injecting side that is positioned at the opposite side of the link region. Thus, the sealant pattern coated on the link region has a height lower than a height of the sealant pattern coated on the liquid crystal injecting side of the etching region having a step. As a result, since the height of the sealant pattern is different according to the position of the LCD device, the cell gap is not uniform and accordingly, brightness is not uniform. Therefore, dummy patterns may be provided among gate link portions and data link portions on which the sealant pattern is coated, thereby preventing non-uniformity in brightness.
FIG. 7 is a plan view a liquid crystal display device according to the related art. In FIG. 7, a liquid crystal display panel is divided into an active region “A” and a sealant region “S”, and cell gaps are uniformly formed by having a dummy pattern 9 larger than a width of a sealant pattern 30 within the region where the sealant pattern is coated. However, as the dummy pattern 9 is formed wider than the width of the sealant pattern 30, the dummy pattern 9 provides a passage through which sealant material 11, which is not hardened, flows into the active region “A”. Accordingly, the sealant material 11 that flows into the active region “A” through the dummy pattern 9 reacts with the liquid crystal material and generates spots on a display screen.